LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY stage IS
   GENERIC( 
      s : integer
   );
   PORT( 
      enable_stage      : IN     std_logic;
      fpga_clk          : IN     std_logic;
      fpga_reset_n      : IN     std_logic;
      rom_im            : IN     integer RANGE 8388607 DOWNTO -8388608;
      rom_re            : IN     integer RANGE 8388607 DOWNTO -8388608;
      x_im              : IN     integer RANGE 8388607 DOWNTO -8388608;
      x_re              : IN     integer RANGE 8388607 DOWNTO -8388608;
      enable_next_stage : OUT    std_logic;
      fi                : OUT    integer RANGE 255 DOWNTO 0;
      y_im              : OUT    integer RANGE 8388607 DOWNTO -8388608;
      y_re              : OUT    integer RANGE 8388607 DOWNTO -8388608
   );
END stage ;

--
ARCHITECTURE arch OF stage IS
BEGIN
END ARCHITECTURE arch;

